Negabinary adders and subtractors



June 18, 1968 M. P. DEREGT 3,389,245

NEGABINARY ADDERS AND SUBTRACTORS I Filed Sept. 10. 1965 6 Sheets-Sheet 1 TRIGGER RESET 1 rSET A NOR q? R T s l S=AD A A l 0 i s L l NOR CIRCUIT Z A DELAY LINE R-s-T FLI P'FLOP T D T T I T 4"- AD HA AD HA AD HC A00 A60 AQD HALF-ADDER HALF-SUBTRACTOR HALF-CO-ADDER F1715 E7115 1]- Y W T "T B 0-, 4AND i AN r +1 CARRY- 'H 1-1 CARRY-IN CARRY- 1 Ti I IN OR CARRY-l OR OUT M ICOUNT-UP OUT I M Ecoum oowu 1 O l I I O l I l l I l I L W. JL 1E J L lk. A

v j AI Ai Ai Ai NEGABINARY COUNTER STAGE NEGABINARY COUNTER STAGE UP FOR EVEN i UP FOR ODDi oowu FOR ODDi DOWN FOR EVENi INVENTOR f1 7. EA .2 3 7. 5.5

MAURITS PIETER DEREGT ATTORNEYS June 18, 1968 M. P. DEREGT 3,3 9,245

NEGABINARY ADDERS AND SUBTRACTORS Filed Sept. 10. 1965 6 Sheets-Sheet z 235| B 4 AND:

234| I 233 cm AND B; I LI: i I 232 OR I i 236- Ti 1 2m NEGABINARY I Ai A l UP-DOWN 0 t COUNTER STAGE J F? a:

l A A B3 C2 C0 0 u T-UP AND I AND 2 AND AND 5 Q Q I RESET J J I A SIGNAL 3 A 2 A l A 0 0 l O l O I O I OVERFLOW SIGNAL FOUR-STAGE NEGABINARY UP-COUNTER c a c B 3 f f o COUNT-DOWN AND AND AND AND $|GNAL RESET 4 I ,l SIGNAL s A 2 A l A 0 OVERFLOW SIGNAL FOUR-STAGE NEGABINARY DOWN COUNTER i J INVENTOR A MAURITS PIETER DEREGT ATTORNEYS June 18, 1968 M. P. DEREGT 8 NEGABINARY ADDERS AND SUBTRACTORS Filed Sept. 10. 1965 6 Sheets-Sheet 3 r- -I I I I AND I I Q- I CARRYI L Ci OUT I In CARRY-IN I I OR COUNT-UP AND Ti 0 LSIGNAL I I I m A A go I QUATERNARY I UP-COUNTER I I STAGE I W I F1 .3A 1 v I m 1,. m m

I T in L AN F D- I CARRY I OUT I I I CARRY- IN on I AND LCOUNTDOWN SIG- I I w I QUATERNARY I A A A DOWN COUNTER I 1 STAGE I F1 3.5 L L J I v AL: AI, i,o i o INVENT OR MAURITS PIETER DEREG'T ATTORNEYS June 18, 1968 M. P. DEREGT 3,389,245

NEGABINARY ADDEHS AND SUBTRACTORS Filed Sept. 10. 1965 s sheets-sheet 4 I 342 335 L m I F NOR L CARRY-IN I CARRY- I337 0R COUNT-DOWN OUT SIGNAL l I 343 334? 34|\L Ci 0 NOR +1 CARRY m 1338 NOR I oFz COUNlT-UP v SIGNAL I NOR OR -336 339- 33 i 332 J l A A A I O l O QUATERNARY I I UP'DOWN I COUNTER I STAGE L i a 7. y y I m ALI i,o i,o

m +--IAND CARRY-IN OR CARRY'OUT I I COUNT-DOWN |l AND SIGNAL m I --AN T T 'HCARRY'OUTI I SCARRYAN I I 0R COUNT'UP I SIGNAL I OR OR I I I l A A I A ALO I n a n l I QUATERNARY I I UP-DOWN I I COUNTER L I STAGE .1L .lL -1-- L-- INVENTOR i 1 1317 II v I I! m m m m MAURITS PIETER DEREGT June 18, 1968 Filed Sept. 10, 1965 M. P. DEREGT NEGABINARY ADDERS AND SUBTRACTORS 6 Sheets-Sheet 5 CONTROL 1 SIGNAL I I i I y I I +ICARRY'IN NOR I SIGNAL I C C. n L4 I C i I r Ti HcARRY-IN m L: I SIGNAL +1 I M I CSR1I3Y-} l o I I u NEGABIINARY NOR NOR l ICOMPLEMENTER l l L JREGISTER STAGE I NEGABINARY l l COMPLEMENTER 3}" "A; j I N R 1 17.44

| I L L I l A 0 i 5o|-\ -5o2 503 504 ]so7 I 1/ 505 w IL IJ 1 I II 'CI I I 508 5067 522 NOR 5gg-NOR OR 523' i I I I r I I 526\NOR 524 NOR 525NOR I an I I 'II sis I I I H I 530 NOR 521 NOR szzuon 529mm: I ADDER I J [suBTRAcToR] BM I NETWORK 532- on s3|- NOR 1- 5n 5|2 I L INVENTOR Dif ATTORNEYS United States Patent 3,389,245 NEGABINARY ADDERS AND SUBTRACTORS Maurits Pieter Deregt, 6528 Jay Miller Drive, Falls Church, Va. 22041 Continuation-impart of application Ser. No. 389,760, Aug. 14, 1964. This application Sept. 10, 1965, Ser. No. 486,347

5 Claims. (Cl. 235175) ABSTRACT OF THE DISCLOSURE An apparatus using electronic, fluidic, cryogenic or other means for performing arithmetic operations upon two numbers expressed in negative radix notation, wherein the choice of operation may depend on the interconnection and arrangement of a plurality of identical logic circuits, or on the nature of the input signals and the choice of output terminals of each of a plurality of identical stages, or on externally-applied control signals to each of a plurality of identical stages. The apparatus also provides for detection of both negative and positive register overflow situations by appending either two additional identical stages, or two special stages.

This application is a continuation-in-part of copending application Ser. No. 389,760, filed Aug. 14, 1964.

This invention relates to calculating elements for digital computers, including those commonly known as general purpose computers (GPC) and digital differential analyzers (DDA). Although these calculating elements are spoken of as though part of an electronic computing apparatus, it will be recognized that they may be used in computing apparatus making use of information storing devices, logic devices and information-carrying signals other than electronic. The devices described in Ser. No. 389,760 are for computation in a number system whose radix is 2. This system will be referred to hereinafter as the negabinary system and numbers expressed in that system will be referred to as negabinary numbers. The explanation of such systems included in application Ser. No. 389,760 will not be repeated in this application. The outstanding characteristic of the negabinary and negabinary-coded systems is the simplification in computer circuitry made possible by the elimination of the sign or polarity-indicating conventions necessary in number systems currently in use.

Still another object of this invention is to provide a circuit which will perform the function of either an adder or of a subtractor, the only difference being in Whether the true or false Boolean value of the addend or minuend digit is selected as one input. Still another object is to provide an adder-subtractor, making use of the same circuit, such that the desired operation may be selected with given control signals.

Each of the foregoing described circuits may be joined with identical units to provide means of obtaining arithmetic sums and differences of negabinary numbers each comprising a multiplicity of digits. Still another object of this invention is to provide such circuits, each comprising a multiplicity of stages to operate upon complete negabinary numbers in true form, to produce resulting negabinary numbers also in true form.

Logic circuits, comprising the circuits referred to above, are described in many reference works. Examples of computer circuits using AND and OR logic elements are given in Arithmetic Operations in Digital Computers, by R. K. Richards, published in 1955 by D. Van Nostrand Company. A list of these and other logic circuits is given on page 160 of Digital Computer Design Fundamentals, by Yaohan Chu, published by the McGraw-Hill Book Co., Inc., in 1962. Various embodiments of these logic circuits are given on pages 160-307. Embodiments making use of fluid means of transferring signals are explained on pages -88 of the December 1964 issue of the Scientific Amerrcan.

Computer circuits comprising logic elements can be synthesized by using Boolean Algebra. This method, which is used to develop and synthesize the circuits previously mentioned, is fully explained on pages 26-50 of Richards and on pages 89-132 of Chu. The Boolean functions referred to in the following explanations will be given in both canonical and in minimized sum-of-products form. The minimization of Boolean functions is fully explained in pages 136-156 of Chu.

As explained on these pages, each Boolean function may be represented in a graphical manner by making use of a Vietch diagram (also called a Karnough map). While only one Vietch diagram corresponds to a given Boolean function, the function itself can be expressed in many different algebraic forms. Each algebraic form corresponds to a mechanization of AND, OR, and NOT logic circuits, as explained on page 33 of Richards text. Likewise, each Boolean function may be mechanized using other logic circuits such as NOR or NAND.

The truth table for some common logic operations, and their symbols, for two Boolean variables is shown in Table I.

From Table I below, the following Boolean algebraic functions can be written:

Each Boolean variable refers to a signal which is an input to or an output from a circuit mechanization to perform a given arithmetic function. There is one basic variable for each operand; for each digit, the basic variable will be subscripted with a number indicative of the digit position. To simplify notation, however, the Boolean functions in general will be written Without subscripts. The variables on the right-hand side of the equal sign are inputs to the corresponding circuit; the variable on the left is an output. Thus, to write the corresponding Boolean function with subscripts, place an i as subscript to all unsubscripted variables and replace the subscript out" with 1' +1.

Example:

R=A 89D out= as used to express Boolean functions is identical to:

1= 1 1 i-l-1 i :l

which are the functions using the symbols of the diagrams. In the discussion and diagrams, the notation used in referring to operands and stages is directly related to the 3 mathematical notation commonly used to describe positional number systems. Hence, A (i=0) represents the low order digit (the units digit); A represents the first digit to the right of the radix point; A represents the high order digit of an n-digit number.

Symbol: Meaning A, A Augend, Minuend, or a first operand. D, D Addend, Subtrahend, or a second operand. K, K A third operand. L, L; A fourth operand. B, B Carry-in of 1 3 orrow) to Stage i. C, C; Carry-in of +1 (Qarry) to Stage 1'. Bout, B Carry-out of 1 from Stage i. out, C Carry-out of +1 from Stage i. R Input to R (reset) terminal of R-S or R-S-T flipflop; Boolean complement of true circuit output.

S, S Input to S (set) terminal of R-S or R-S-T flipflop; true output of sum, difference, or result of circuit operation.

T, T Input to T (trigger) terminal of T or R-S-T flipflop; output of circuit to operate T terminal of a N, N; Negative Detect Carry-in to odd stage.

P, P Positive Detect Carry-in to even stage.

Add Control signal for addition:

Add.

Sub Control signal for subtraction:

Subtract.

i, i Stage or order number, corresponding to the power of the radix of the digit position.

It or m The total number of digits in an operand.

In describing counters and other devices using bi-stable state storage registers, R-S-T flipflops will be used, since the operation of these flipflops is easy to trace. A signal at the R input terminal (RESET) will cause the flipflop to be reset to the ZERO value; a signal at the S input terminal (SET) will cause the flipflop to assume the ONE value; and a signal at the T terminal (TRIGGER) will cause the flipflop to change its value. The operation of this and the T, the R-S, and the J-K fiipflops is explained more fully on pages 127-130 of Chu.

Several embodiments of the invention referred to above,

making use of NOR and other logic circuits and R-S-T flipflops, are described hereinbelow and are shown in the drawings. It is understood that these drawings are illustrations and examples of preferred embodiments of the invention; they are not definitions of limits of the invention.

FIGURE 1A shows the symbol for the NOR logic module, together with the Boolean function variables as inputs and output;

FIGURE 1B shows the symbol which will be used herein to represent R-S-T flipflop;

FIGURE 1C is the symbol for a delay line, in which the output signal is identical to the input signal but occurs a fixed time interval later;

FIGURE 1D is the symbol for a binary half-adder, which preforms the arithmetic function A+D on corresponding digits of the binary operands, producing a binary sum output digit and a carry output;

FIGURE 1B is the symbol for a binary half-subtractor, which performs the arithmetic function AD on corresponding digits of the binary operands, producing a sum output digit and a carry output;

FIGURE 1F is the symbol which will be used herein to represent the circuit for a negabinary half-co-adder, described more fully hereinafter, which performs th arithmetic function (A +D) on the corresponding digits of the negabinary operands, producing the negation of the signal representative of the sum digit, the negation of the signal representive of the carry digit, and a third output signal;

FIGURE 2A is a block diagram of one stage of a negabinary up-counter;

FIGURE 23 is a block diagram of one stage of a negabinary down-counter;

I FIGURE 2C is a block diagram of one stage of a negabinary up-down counter;

FIGURE 2D is a block diagram of four stages of a parallel negabinary up-counter illustrating the overflow and RESET signal circuitry;

FIGURE 2B is a block diagram of four stages of a parallel negabinary down-counter;

FIGURE 3A is a block diagram of one stage of a quaternary up-counter in which a two-bit negabinary code is used to represent the four quaternary digits 2, 1,

FIGURE 3B is a block diagram of one stage of a quarternary down-counter;

FIGURE 3C is a block diagram of one stage of a quarternary up-down counter;

FIGURE 3D is a block diagram of one stage of a second quarternary up-down counter;

FIGURE 4A is one stage of a negabinary complementing circuit using NOR logic modules;

FIGURE 4B is a block diagram of one stage of multistage register comprising R-S-T registers and logic circuitry to complement a multi-digit negabinary number stored in the register;

FIGURE 5 is a block diagram of a logic network capable of performing either negabinary addition or subtraction upon corresponding digits of two negabinary operands and a carry-in digit;

FIGURE 6A is a block diagram of a negabinary full adder-subtractor;

FIGURE 6B is a block diagram of the overflow stages of a negabinary adder-subtractor;

FIGURE 7A is a block diagram of a negabinary half co-adder;

FIGURE 7B is a block diagram of a negabinary full co-adder comprising a binary half-adder, a binary halfsubtractor, and an OR circuit;

FIGURE 7C is a block diagram of a negabinary full co-adder comprising two negabinary half co-adders and an OR circuit.

It will be understood that FIGS. 1A to 1F, inclusive, illustrate symbols which are used in other figures of the drawings and do not illustrate computer circuits forming part of the invention. The foregoing description and explanation of these figures are therefore believed to be sufiicient for the purposes of this specification and the appended claims.

NEGABIZNARY CODED QUATERNARY NOTATION In negabinary notation, a sequence of four digits d d d d d represents the quantity These terms can be grouped in pairs; numbers with an odd quantity of digits can be preceded by a zero.

These terms can be factored to give the following expression:

Each pair of negabinary digits thus can be considered to represent one digit in the system whose base is +4, which is the quaternary scale of notation. There are four combinations of two negabinary digits; these have the decimal values shown in Table II.

TABLE II Negabinary Decimal Quaternary Digits Value Digits The four digits of this binary-coded quaternary systern are thus 2, 1, 0, +1, represented respectively by E, I, 0, 1. Any negabinary number can be considered a quaternary number but thus pairing 01f negabinary digits starting with the radix point. Thus the negabinary number 10, 001, 101, can be paired off to 10, 00, 11, 01, which is the negabinary-coded equivalent for the quaternary number 0I1z This is equal to 131 in decimal notation.

It is evident that a negabinary coded number system uses two bases: the primary system in which the digits are in the encoded form; and the secondary or auxiliary system, in which each digit of the primary system is encoded by means of negabinary digits. It is convenient, therefore, to extend the previous notation used to designate operands and stages. This will be done by using the subscript i to denote a digit position in the primary system, and adding the subscript f to indicate a digit position in the secondary system, such that j is the power of the secondary radix of that position. A negabinary coded quaternary number of four digits may thus be designated 3. 1 3, o z, 1 2, 0 r, l l, a o, 1 0, o in which each pair of negabinary digits comprise one quaternary digit.

Although this system has a positive base, it makes use of digits with intrinsically negative value; therefore, the same advantages of not requiring separate sign conventions and algorithms apply. This suggests computer circuits based on the quaternary system (+4), the negoctal (8), the hexadecimal (+16) and others, having the identical advantages of a negabinary system. Certain of the circuits of the present invention are based on this system.

If the negabinary system upon which the quaternary code is based makes use of digits having the values 0 and -1 instead of 0 and +1, as developed above, the digits of the quaternary system would be 1, 0, 1, 2.

ARITHMETIC OPERATIONS The operations to be considered in the present invention include counting, complementation, addition, and subtraction.

Counting As in normal binary, the number of combinations which it bits can assume is 2. In negabinary notation, some of these will have a negative value, some a positive. In order to proceed through all possible combinations in sequence without overflow, the counting process must start with the representation of lowest value. In normal binary, this is a string of zeroes. In negabinary, it is a string of alternating 1s and Os with the 1s in odd i positions. Table III gives the full sequence for n=3, with normal binary and decimal equivalents.

TABLE III Decimal Binary N egabinary Value While Table III gives the numerical values for the proper sequences, it provides but few clues on the behavior of these counting sequences. A more revealing array is given in Table IV, in which n=4. S(r) denotes the num ber system whose radix is r; S(10) denotes the decimal system, S(2) denotes binary, and S(2) denotes negabinary.

In each column of Table IV, application of the appropriate counting or sequencing algorithm to the bottom representation should result in the one at the top of the column, with an overflow of one into the next left position. It can now be seen that in the two columns, the digits TABLE IV Negabinary Binary are identical for even i, and complementary for odd i. Therefore, for odd i in S(-2), the counting algorithm is the same as that for 8(2); and for even i, the counting algorithm is the inverse of that for 8(2), the count operation always causes a change in the low order position, for which i=0, (even). The full algorithm, for both upand down-counting, is given in Table V; d; is the next lowerorder digit.

TABLE V Change 11; 1 Change in Up: Downcountmg counting 0 yes yes odd 0 to 1 no yes 0 to 0 yes no even 0 to 1 yes no 1 to 0 no yes Negabinary counters receive the count-down pulse, while correspondingly the C carry-in terminal of the low-order stage is used to receive the count-up pulse.

The canonical form of the sum-of-products Boolean functions are:

S=AF+ZBU+ZFC B =AFC C =ZBU T =ZBU+ABU+ZFC+AFC BC= The minimized Boolean algebraic functions are:

One stage of a negabinary up-down counter which mechanizes these functions by means of AND-OR logic circuit is shown in FIGURE 2C.

In FIGURE 2C, the digit A, for the ith position is stored in register 211. Carry-in signals for +1 and --1 carry-in from the next lower stage are applied respectively to input terminals 232 and 233; if terminals 232 and 233 are used for counting input signals, then the value of --1 for B, or +1 for C must be multiplied by (2)i to obtain the true numerical value. For example, a pulse applied to terminal 233 of stage i=1 has the value +2. Signals representing carry-out signals for +1 and 1 carry-outs to the next higher stage are available at output terminals 234 and 235 respectively. The trigger signal output 236 is applied to the T-input terminal of register 231, which then assumes the new correct state to represent the ith digit.

The Boolean functions representing the output of each of the logic circuits shown on FIGURE 2C is as follows:

If the stage under consideration is the high order stage (i=n-1), then the signals B and C available at output terminals 234 and 235 represent overflow signals for up-counting and down-counting, respectively for an even number of stages, and for down-counting and up counting respectively, for a counter comprising an odd number of stages. These overflow properties, which are uncomplicated by polarity representations, permit great simplifications in the design of computing elements for digital differential analysers (DDAs).

Examinations of the Boolean functions for B and C show that, on tip-counting, the low-order stage (i=0) can only have a -1 carry-out (or none); that i=1 stage consequently can have only a +1 carry-out (or none); and so on alternately. The carry-out of even stages of an up-counter is thus always B =AC, and of odd stages, C =ZB. In down-counting, the reverse is true. Counter stages for each of these possibilities are shown in FIGURES 2A and 2B. Since there is only one carry-in input possibility, the trigger signal has the same value as the carry-in signal. An up-counter of four stages, designed in accordance with these principles, is illustrated in FIGURE 2D; a four-stage down-counter is illustrated in FIGURE 2E. The reset signals shown are such as to set two initial numbers to 1010 and 0101, respectively.

QUATERNARY COUNTER All of the counters previously discussed were negabinary; that is, each circuit was designed to provide for the computation of one digit of a negabinary number. Computation can be speeded up with little or no increase in components or complexity by the use of circuits which compute two negabinary digits. This type of circuit is in effect based on a quaternary system of notation in which the base or radix is positive four. Since the digits of this system are coded by two negabinary digits, the digit values are 2, 1, 0 and +1, respectively, for the negabinary digit pairs 10, ll, 00, and 01. In a counter, each quaternary digit is stored in a pair of fiipflops.

Table VII presents the truth table for up-down counting in this system.

TABLE VII Symbol Variable Value Function Diagram Even Digit An Am 0101 0101 0101 0101 Odd Digit A A5,; 0011 0011 0011 0011 1 Carry-in B Ba 0000 1111 0000 1111 +1 Carry-in C C; 0000 0000 1111 1111 Decimal Sum 012-1 T05 1210 Even Sum Digit So Sm 0101 1010 1010 0000 Odd Sum Digit Si Sm 0011 1001 0110 0000 Even Trigger To Tao 0000 1111 1111 0050 Odd Trigger T1 Tm 0000 1010 0101 0000 1 Carry-out out Bi-H 0000 0010 0000 0000 +1 Carry-out Gout Cm 0000 0000 0100 0000 As in the case of the negabinary counter, the 0s indicate that BC=0; B and C represent the count-down and count-up signals respectively.

The canonical form of sum-of-products Boolean functions are as follows (the isubscripts are omitted):

One stage of an up-down quaternary counter using NOR-OR logic elements and R-S-T flipfiops, which mechanizes these Boolean functions is illustrated in 9 FIGURE 30. The negabinary code of two bits for the quaternary digit is stored in flipfiop registers 331 and 332. The Boolean function for the value of the output of each NOR-OR gate in the circuit of FIGURE 3C is as follows:

334; z +c= A u 336: Zr +0 (A +B)= Z B+A C 337: Z A B 338: A0216 339; B+C= B l-C It will be seen in FIGURE 3C that the input signals B and C, are applied respectively to input terminals 340 and 341. Input signal B may be a 1 carry-in from the next lower stage, or it may be a count-down signal, and input signal C; may be a +1 carry-in from the next lower stage, or it may be a count-up signal. The value of the count signal is +1 or 1 for C and B respectively, multiplied by (4 for example, a count pulse applied to terminal 340 of a stage for which i=2 would have the value 4. The output of OR circuit 339 is seen to have the value for T and is therefore used to trigger flip-flop A while T is available at the output of NOR circuit 336 to trigger flip-flop A Values for B1111 and C are equal to the outputs of NOR circuit 337 and 338 respectively and are available at output terminals 342 and 343 respectively. Information may be read into or from the storage registers A and A in ways well known to those versed in the art.

It was demonstrated in the case of negabinary counters that tip-only or down-only counters could have only one non-zero carry-in or carry-out, and this holds true also in quaternary.

The minimized equations for a quaternary counter stage capable of counting up from 2 to +1, and generating a carry-out signal of +1 in counting up from +1 to 2, are as follows:

A quaternary stage which mechanizes these equations is shown in FIGURE 3A. FIGURE 3B shows a quaternary down counter, for which the minimized Boolean functions are:

1 4 out= 0 1 Complem enters A brief discussion on complementation of negabinary numbers was presented in the co-pending application The sum-of-product canonical Boolean functions are;

S=AU+ZC T=ZC+AC out= Minimized, these functions become:

S :A C T: C out= A circuit which mechanizes these functions by means of NOR logic elements is shown in FIGURE 4A. It will be noted that four NOR elements are required, with one logic level for the carry-out signal and three for the result digit signal. It will be noted also that the false value of the operand signal rather than the true is required for input.

A complementing circuit making use of NOR and AND logic elements and storage registers is shown in FIGURE 4B. This also has only one level per stage for the carry logic.

A ddition The rules for addition of two digits, without a carry, are as follows:

With a carry of -1 the rules are:

With a carry of +1 the rules are:

It is clear that a carry of +1 and a carry of -1 cannot both be generated simultaneously. This makes possible a circuit simplification of the Boolean functions for addition, represented by the Boolean function BC=0, where B is a carry-in of l and C is a carry-in of +1.

This is represented in the truth table for addition, Table IX by 0, since values here may be either 0 or 1.

TABLE IX Carry-In Variable Symbol None -1 +1 Both Augend Digit A 0101 0101 0101 0101 Augend Digit D 0011 0011 0011 0011 Carry-In B 0000 1111 0000 1111 +Carry-In O 0000 0000 1111 1111 Decimal Sum 0112 1001 1223 Result Digit S 0110 1001 1001 B000 Trigger Signal T 0011 1100 1100 00091 Carry-Ont B, M 0001 0000 0111 0000 +Carry-Out C.) t 0000 1000 0000 01100 The Boolean algebraic functions for Truth Table IX in canonical surn-of-products form are:

After minimization, they are:

While a circuit to mechanize these functions is readily synthesized by means of AND, OR and NOT logic elements, FIGURE shows a circuit making use of two OR circuits and ten NOR circuits.

In FIGURE 5, the signals A, (501) and D, (502) mp resenting the ith negabinary digits (the least significant digits are the zero-th digits) of the augend and addend respectively are applied to terminals 503 and 504. The signals B (505) and C (506) representing the l and +1 carry-ins from the next lower stage are applied respectively to input terminals 507 and 508; and corresponding carry-outs B (514) and C (513) at output terminals 516 and 515. The result function output Sum (510) and its complement Sum, (509) are available at terminals 512 and 511 respectively. It should be noted that OR circuit 523 can be eliminated by bundling the input signals available at terminals 507 and 508 at NOR circuits 524, 525 and 527. Bundling is described on pages 128 and 129 of the book The Logical Design of Transistor Digital Computers, by Gerald A. Maley and John Earle, published in 1963 by Prentice-Hall, Inc.

The NOR circuit 521 is considered as a single NOR circuit, for purposes of identification, while NOR circuits 524 and 525 comprise a pair and NOR circuits 527, 528 and 529 comprise a triplet or triad.

The Boolean functions representing the output of each of the logic elements in FIGURE 5 are as follows:

If the complement of the sum digit is not required, OR r circuit 532 may be deleted. This and other minor variations to the circuit will come readily to the mind of those skilled in the art; such variations are considered to be within the spirit and scope of the present invention.

Examples follow of negabinary addition such as would be performed by eight stages of an adder such as that illustrated in FIGURE 5. Numbers below the sum line represent overflow positions.

Overflow 11 256 True Sum 175 Since 1, 0, and 1 are possible carries, a carry-out of the high order stage of either +1 or 1 represents an overflow condition. With the radix point at the extreme right, an overflow of either +1 (01) or 1 (11) means the register is storing an incorrect result which differs from the correct one by the value of the overflow times (2). For n=8, (-2) is +256.

Subtraction As in addition, subtraction results in true representation regardless of the magnitudes and polarities of the operands, and overflow is handled by shifting and scaling accordingly. Subtraction can be accomplished by adding the arithmetic complement of the subtrahend. One of the complementing circuits previously described can be used for this, so as to form with the adder, the arithmetic function S=A+ D)-=A D.

Following the pattern used in addition, the rules for subtraction in negabinary are as follows:

No carry:

00=0 0-1'=1, carry +1 10=1 11=0 Carry:

00+1=1 01+1=0 1O+1'=0, carry 1 1-1+1=1 Carry:

001-=1, carry +1 0-11=0, carry +1 10-1=0 1-1-1=1, carry +1 These rules are summarized in Table X. As in the case of addition, BC=0.

TABLE X Binary Value Variable Symbol No Carry -1 +1 Both Mlnuend Digit. A 0101 0101 0101 0101 Subtrahend Digit D 0011 0011 0011 0011 Carry-In B 0000 1111 0000 1111 +Carry-In C 0000 0000 1111 1111 Decimal Difference 0110 1071 1201 Result Digit S 0110 1001 1001 0000 Trigger SigrmL- T 0011 1100 1100 0000 Carry-Out. B n t 0000 0000 0100 0000 +Carry-Out Con 0010 1011 0000 0000 Comparison of Table X with Table 1X for addition will show that the functions for S and T are identical for addition and subtraction, and hence are described by the identical Boolean functions. The sum-of-products canonical forms for the carry-out functions are as follows:

B g=ABCF C =IEUD+ZBUF+ZBFD+ABUD After minimization, these are:

While many different circuits may be synthesized from these Boolean functions, the circuit previously described for negabinary addition and illustrated in FIGURE 5 may be used, provided that certain changes are made in labeling the input and output terminals. These changes are given in the brackets in FIGURE 5, and are as follows:

Terminal: Signal 512 K in lieu of A (complement of minuend in lieu of augend). 503 C in lieu of B 507 B in lieu of C 508 B1+1 111 11611 Of CH1. 515 CH4 111 lieu Of Bu 516 Dif in lieu of u m 511 Fif in lieu of Sum Considering the bracketed labels in FIGURE 5, the signal [A (501) representing the complement of the ith negabinary digit of the minuend and [D] (502) representing the ith negabinary digit of the subtrahend are applied to terminals 503 and 504. The signals [C (505) and [B (506) representing +1 and --1 carry-ins from the next lower stage are applied respectively to input terminals 507 and 508. The result function output [Dif,] (509) and its complement [Fif (510) are available at output terminals 511 and 512 respectively. The carry-out signals for +1, [C (514), is available at output terminal 516; that for l, [E (513), at 515.

That the same circuit may be used for both negabinary addition and subtraction is easily demonstrated by interchanging S and S, A and K, and B and C, in the Boolean functions for addition. This gives:

S 1100 1001 71 Overflow 1 +256 True Value +185 the discussion of overflow given for addition is applicable as well to subtraction. However, in the circuit of FIGURE 5, care must be exercised in the interpretation of the overflow signals available at carry-out out-put terminals 515 and 516 of the highest-order stage, which depends on whether the circuit is being used for addition or subtraction (B and C are interchanged).

This property of the adder circuit to be used as a subtractor is potentially of great utility in a DDA, which patchboard wiring can be used to make an integrator have a true or arithmetic complement output.

Co-Addition A half-coadder is illustrated in FIG. 7A. It is a logic circuit rather than an arithmetic circuit and is so called because two such circuits arranged with an OR circuit as illustrated in FIG. 7C perform the arithmetic operation of co-addition on a pair of digits of two negative binary operands. This operation may be defined as that which produces the additive inverse of the sum of the operands, or R in the definition R'==(A+B). Full coadder circuits may, in turn, be aranged in combination to perform addition, subtraction, or any combination of addition and subtraction on a plurality of operands, as disclosed in my co-pending application Ser. No. 389,760.

Another embodiment of a full negabinary co-adder circuit is shoWn in FIG. 7B, wherein a conventional binary half-adder and a half-subtractor are used in combination with an OR circuit.

Additional embodiments of the invention in this specification will occur to others and therefore it is intended that the scope of the invention be limited only by the appended claims and not by the embodiment described hereinabove. Accordingly, reference should be made to the following claims in determining the full scope of the invention.

What is claimed is:

1. Negative binary digital arithmetic system for adding or subtracting a pair of numerical values each represented by plural negative binary input signals ranging in sequence to represent negative binary digits from most significant to least significant orders, comprising a plurality of arithmetic circuits each having control input terminals for receiving an Add" control signal and a Sub control signal, digit input terminals for receiving digit signals A and D representing negative binary digits of one order and carry input terminals for receiving carry signals B and C from the next lower order, each of said arithmetic circuits including means for producing resultant output signals Dif and Sum representative of the difference digit or the sum digit of the received negative binary input signals and carry signals B and C and means for connecting the said arithmetic circuits in a serial sequence in which the carry signals from each arithmetic circuit are applied to the carry terminals of the next order arithmetic circuit, said signal-producing means satisfying the Boolean functions:

Dif= (A -Add-+Z-Sub) es (B -i-C) on] Sub Sum: [(A -Add+Z-Sub) ea 3+0) @1 1 B,,,,,= (A Add-l-Z-Sub) -C+C-D where the dot signifies the logical AND function, the plus sign signifies the logical OR function, and the bar indicates the logical inverse of a variable, and G9 signifies the logical EXCLUSIVE OR function.

2. The apparatus according to claim 1, wherein said system is extended by two arithmetic circuits in addition to those required for said orders, each of which comprises one overflow stage of an overflow network.

3. The apparatus according to claim 1, wherein said signal-producing means comprises a first NOR circuit, a second NOR circuit connected to said first NOR circuit and to said digit input terminals, a third NOR circuit connected to said digit input terminals, an OR circuit connected to said carry input terminals, a pair of NOR circuits each connected to one of said digit input terminals and to said OR and third NOR circuits, a NOR circuit connected to one of said carry input terminals and to said third and said pair of NOR circuits and producing a carry signal, a triad of NOR circuits one of which is connected to said OR circuit and said pair of NOR circuits, second of said triad is connected to one of said digit input terminals and to said third and one of said pair of NOR circuits, and the last of said triad is connected to the other of said digit input terminals and to said third and other of said pair of NOR circuits, and an OR and a NOR circuit each connected to each of said triad and producing said resultant output signals.

4. A full negabinary complementary adder comprising a pair of identical half co-adders each producing output signals, input terminals for receiving input signals representative of corresponding operand digits and a carryin signal from a lower order, means for producing a carryout signal in response to signals received from each of said half co-adders, one of said half co-adders producing an output signal representative of the co-sum digit in response to the said carry-in signal and a signal from other of said half co-adders.

5. A full negabinary complementary adder comprising a binary half adder and a binary half subtractor each producing output signals, input terminals for receiving digit input signals and a carry-in signal from a lower order, means for producing a carry-out signal in response to signals received from the said half adder and half subtractor, the said half subtractor producing an output signal representative of the co-sum digit in response to the said carry-in signal and a signal from the said half adder.

References Cited UNITED STATES PATENTS 3/1963 Keir et a1. 235 1/1967 Coates et a1 235173 

